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Lattice Semiconductor MachXO2 User Manual

Other manuals for MachXO2: User Manual
Manual is about: LPDDR SDRAM Controller IP Core

Summary of MachXO2

  • Page 1

    October 2012 ipug92_01.2 machxo2 lpddr sdram controller ip core user’s guide.

  • Page 2: Table of Contents

    © 2012 lattice semiconductor corp. All lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.Latticesemi.Com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are s...

  • Page 3

    Table of contents ipug92_01.2, october 2012 3 lpddr sdram controller user’s guide getting started .................................................................................................................................................... 20 chapter 4. Ip core generation........................

  • Page 4: Introduction

    Ipug92_01.2, october 2012 4 lpddr sdram controller user’s guide introduction the lpddr synchronous dynamic random access memory (sdram) controller is a general-purpose memory controller that interfaces with industry standard lpddr memory devices/modules compliant with jesd209b, lpddr sdram standard,...

  • Page 5: Functional Description

    Ipug92_01.2, october 2012 5 lpddr sdram controller user’s guide overview the lpddr memory controller consists of two major parts: the controller core logic module and the i/o logic mod- ule. This section briefly describes the operation of each of these modules. Figure 2-1 provides a high-level block...

  • Page 6

    Functional description ipug92_01.2, october 2012 6 lpddr sdram controller user’s guide this module is automatically activated at the exit of a deep power down operation and the lpddr memory is re-ini- tialized. I/o training block the i/o training block adjusts the machxo2 i/os for write/read operati...

  • Page 7

    Functional description ipug92_01.2, october 2012 7 lpddr sdram controller user’s guide table 2-2 describes the user interface signals at the top level i/o for wishbone interface. Data_mask[(dsize/8)-1:0] n/a input data mask input for write_data. Sclk n/a output system clock output. The user logic us...

  • Page 8

    Functional description ipug92_01.2, october 2012 8 lpddr sdram controller user’s guide using the local user interface the local user interface of the lpddr memory controller ip core consists of five independent functional groups: • initialization control • command and address • data write • data rea...

  • Page 9

    Functional description ipug92_01.2, october 2012 9 lpddr sdram controller user’s guide the user logic that it is ready to receive a command by asserting the cmd_rdy signal for one cycle. If the core finds the cmd_valid signal asserted by the user logic while cmd_rdy is asserted, it takes the cmd inp...

  • Page 10

    Functional description ipug92_01.2, october 2012 10 lpddr sdram controller user’s guide write the user initiates a memory write operation by asserting cmd_valid along with the write or writea command and the address. After the write command is accepted, the memory controller core asserts the datain_...

  • Page 11

    Functional description ipug92_01.2, october 2012 11 lpddr sdram controller user’s guide figure 2-5. User-side read operation reada reada is treated in the same way as a read command except that the core issues a read with auto precharge command to the memory instead of a read command. This makes the...

  • Page 12

    Functional description ipug92_01.2, october 2012 12 lpddr sdram controller user’s guide the memory command mapping of the port_1 wishbone bus are described in table 2-5 . The memory addresses shown in table 2-6 are reserved for the controller and should not used by the port 0 user. Local-to-memory a...

  • Page 13

    Functional description ipug92_01.2, october 2012 13 lpddr sdram controller user’s guide mode register programming the lpddr sdram memory devices are programmed using the mode registers mrs and emrs. The bank address bus (em_ddr_ba) is used to choose one of the mode registers, while the programming d...

  • Page 14: Parameter Settings

    Ipug92_01.2, october 2012 14 lpddr sdram controller user’s guide the ipexpress™ tool is used to create ip and architectural modules in the diamond design software. Table 3-1 pro- vides a list of user-configurable parameters for this ip core. The parameter settings are specified using the lpddr sdram...

  • Page 15

    Parameter settings ipug92_01.2, october 2012 15 lpddr sdram controller user’s guide figure 3-1. Mode options in the ipexpress tool type tab the type tab allows the user to select the lpddr controller configuration for the target memory device and the core functional features. These parameters are co...

  • Page 16

    Parameter settings ipug92_01.2, october 2012 16 lpddr sdram controller user’s guide clock this parameter specifies the frequency of the memory clock to the on-board memory. The frequency is 100 mhz or less. Devices the machxo2 device family provides a lpddr jedec-compliant phy and memory controller....

  • Page 17

    Parameter settings ipug92_01.2, october 2012 17 lpddr sdram controller user’s guide i/o auto training this is an on/off option and if enabled, the controller will train the i/os automatically. Refer to “i/o training” on page 4 for more information. Periodic i/o auto retraining this is an on/off opti...

  • Page 18

    Parameter settings ipug92_01.2, october 2012 18 lpddr sdram controller user’s guide memory device timing tab figure 3-4 shows the contents of the memory device timing tab. Figure 3-4. Memory device timing options in the ipexpress tool the default memory timing parameters displayed in this tab are th...

  • Page 19

    Parameter settings ipug92_01.2, october 2012 19 lpddr sdram controller user’s guide support synplify if selected, ipexpress generates evaluation scripts and other associated files required to synthesize the top-level design using the synopsys synplify synthesis tool. Support modelsim if selected, ip...

  • Page 20: Ip Core Generation

    Ipug92_01.2, october 2012 20 lpddr sdram controller user’s guide this chapter provides information on how to generate the lpddr sdram ip core using the diamond ipexpress tool, and how to include the core in a top-level design. The lpddr sdram ip core can be used in the machxo2 device family. For exa...

  • Page 21

    Ip core generation ipug92_01.2, october 2012 21 lpddr sdram controller user’s guide figure 4-1. Ipexpress dialog box note that if the ipexpress tool is called from within an existing project, project path, design entry, device family and part name default to the specified project parameters. Refer t...

  • Page 22

    Ip core generation ipug92_01.2, october 2012 22 lpddr sdram controller user’s guide ipexpress-created files and top level directory structure when the user clicks the generate button in the ip configuration dialog box, the ip core and supporting files are generated in the specified project path dire...

  • Page 23

    Ip core generation ipug92_01.2, october 2012 23 lpddr sdram controller user’s guide the lpddr sdram controller ip core consists of the following four major functional blocks: • top-level wrapper (rtl) • obfuscated memory controller core for simulation and encrypted netlist memory controller core for...

  • Page 24

    Ip core generation ipug92_01.2, october 2012 24 lpddr sdram controller user’s guide simulation files for ip core evaluation once a lpddr sdram controller ip core is generated, it contains a complete set of test bench files to simulate a few example core activities for evaluation. The simulation envi...

  • Page 25

    Ip core generation ipug92_01.2, october 2012 25 lpddr sdram controller user’s guide evaluation script file modelsim and aldec active-hdl simulation macro script files are included for instant evaluation of the ip core. All required files for simulation are included in the macro script. This simulati...

  • Page 26

    Ip core generation ipug92_01.2, october 2012 26 lpddr sdram controller user’s guide supports the ability to implement the lpddr sdramlpddr_eval core in isolation. Push-button implementation of this top-level design with synplify rtl synthesis is supported via the project files _eval.Ldf located in t...

  • Page 27

    Ip core generation ipug92_01.2, october 2012 27 lpddr sdram controller user’s guide 8. Click generate . 9. Check the generate log tab to check for warnings and error messages. 10.Click close . The ipexpress package file (.Ipx) supported by diamond holds references to all of the elements of the gener...

  • Page 28: Application Support

    Ipug92_01.2, october 2012 28 lpddr sdram controller user’s guide this chapter provides application support information for the machxo2 lpddr sdram controller ip core. Core implementation this section describes the major factors that are important for a successful lpddr memory controller implementa- ...

  • Page 29: Core Verification

    Ipug92_01.2, october 2012 29 lpddr sdram controller user’s guide the functionality of the machxo2 lpddr sdram controller ip core has been verified via simulation with lpddr simulation models from micron technology, including: • simulation environment verifying proper lpddr functionality using lattic...

  • Page 30: Support Resources

    Ipug92_01.2, october 2012 30 lpddr sdram controller user’s guide this chapter contains information about lattice technical support, additional references, and document revision history. Lattice technical support there are a number of ways to receive technical support. Online forums the first place t...

  • Page 31

    Support resources ipug92_01.2, october 2012 31 lpddr sdram controller user’s guide revision history november 2010 initial release. December 2011 updated quick facts table. Updated lpddr core configuration parameters table. Appendix a – updated performance and resource utilization table for machxo2. ...

  • Page 32: Resource Utilization

    Ipug92_01.2, october 2012 32 lpddr sdram controller user’s guide this appendix gives resource utilization information for lattice cplds using the lpddr sdram controller ip core. Ipexpress is the lattice ip configuration utility, and is included as a standard feature of the diamond design software. D...