Lattice Semiconductor MachXO2 User Manual - Table of Contents
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG92_01.2, October 2012
2
LPDDR SDRAM Controller User’s Guide
Chapter 1. Introduction .......................................................................................................................... 4
Introduction ........................................................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Chapter 2. Functional Description ........................................................................................................ 5
Overview ............................................................................................................................................................... 5
Initialization Block......................................................................................................................................... 5
I/O Training Block......................................................................................................................................... 6
Data Control Block ....................................................................................................................................... 6
LPDDR I/Os ................................................................................................................................................. 6
Command Application Logic Block............................................................................................................... 6
Command Decode Logic Block.................................................................................................................... 6
Signal Descriptions ............................................................................................................................................... 6
Using the Local User Interface.............................................................................................................................. 8
Initialization Control...................................................................................................................................... 8
Command and Address ............................................................................................................................... 8
User Commands .......................................................................................................................................... 9
Power Down and Deep Power Down......................................................................................................... 11
User Commands for Wishbone Interface ................................................................................................... 11
Local-to-Memory Address Mapping .................................................................................................................... 12
Mode Register Programming .............................................................................................................................. 13
Chapter 3. Parameter Settings ............................................................................................................ 14
Mode Tab ............................................................................................................................................................ 14
Type Tab ............................................................................................................................................................. 15
Select Memory ........................................................................................................................................... 15
Clock .......................................................................................................................................................... 16
Devices ...................................................................................................................................................... 16
Memory Data Bus Size .............................................................................................................................. 16
Data_rdy to Write Data Delay .................................................................................................................... 16
Clock Width ................................................................................................................................................ 16
Setting Tab.......................................................................................................................................................... 16
Row Size .................................................................................................................................................... 16
Column Size............................................................................................................................................... 16
I/O Auto Training ........................................................................................................................................ 17
Periodic I/O Auto Retraining....................................................................................................................... 17
Partial Array Self Refresh........................................................................................................................... 17
Memory Clock ............................................................................................................................................ 17
Burst Length............................................................................................................................................... 17
CAS Latency .............................................................................................................................................. 17
Burst Type.................................................................................................................................................. 17
Memory Device Timing Tab ................................................................................................................................ 18
Synthesis and Simulation Tab............................................................................................................................. 18
Support Synplify ......................................................................................................................................... 19
Support ModelSim...................................................................................................................................... 19
Support Aldec............................................................................................................................................. 19
Info Tab ............................................................................................................................................................... 19
Memory Interface Pins ........................................................................................................................................ 19
Number of Bi-directional Pins..................................................................................................................... 19
Number of Output Pins............................................................................................................................... 19