N.A.T. NAT-MCH Technical Reference Manual - 3.2 Microcontroller
NAT-MCH HUB-Module PCIe – Technical Reference Manual
Version 1.2
© N.A.T. GmbH
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3.2 Microcontroller
For configuration of the PCIe switch and for providing hot-swap functionality, an 8-bit
Atmel microcontroller resides on the NAT-MCH HUB-Module PCIe. The microcontroller
can be updated by the CPU on the NAT-MCH BASE-Module via SPI interface. Normal
communication between the CPU and the microcontroller is done by IPMI messages over
the I²C interface.
The strapping options and the reset signal of the switch can be controlled by
programming registers in the microcontroller. Also the PCIe Hot-Plug signals can be
served by the microcontroller.
Furthermore, three temperature sensors are connected to a second I²C bus of the
microcontroller. The microcontroller makes these sensors accessible to the CPU on the
NAT-MCH BASE-Module via IPMI.
3.3 FPGA
The Lattice MachXO2 FPGA is used to emulate a set of I
2
C port expanders that the PLX
switch normally uses to extend its pins for PCIe Hotplug support on all ports. The FPGA
implements an I
2
C interface towards the PLX switch and behaves as if there were 12 I
2
C
port expenders connected.
Further it implements a second interface towards the Atmel µC, so that the Hotplug
signals finally can be exchanged with the MCH main firmware.
3.4 Multiplexing Units
There are two PCIe Gen3 compliant multiplexing chips (each can switch two lanes) used
to switch the four lanes going towards AMC12 to the double-width NAT-MCH BASE-
Module. From the BASE-Module these lanes connect to an optional PCIe-capable
module connected as RTM to the double-width BASE-Module.
3.5 PCIe Interfaces
The NAT-MCH HUB-Module PCIe implements interfaces to connect fabrics D to G of up
to 12 AMCs or an optional Root Complex, which is only available on a double-width NAT-
MCH BASE-Module, instead of the 12th AMC.
3.6 Interface to NAT-MCH BASE-Module
The Microcontroller on the NAT-MCH HUB-Module PCIe can be updated by the CPU on
the NAT-MCH BASE-Module via SPI interface. Normal communication between
Microprocessor and CPU is done by IPMI messages via I²C interface.
A configuration EEPROM for the PCIe Switch resides on the NAT-MCH HUB-Module
PCIe. This EEPROM can be programmed / updated by the CPU of the NAT-MCH BASE-
Module via SPI interface.
3.7 Interface to NAT-MCH CLK-Module
The NAT-MCH CLK-Module can provide the 100 MHz PCI Express compliant clock signal
to the NAT-MCH HUB-Module PCIe.