Xilinx Spartan-3E User Manual - Vga Signal Timing
56
Spartan-3E Starter Kit Board User Guide
UG230 (v1.0) March 9, 2006
Chapter 6:
VGA Display Port
R
As shown in
, the VGA controller generates the horizontal sync (HS) and vertical
sync (VS) timings signals and coordinates the delivery of video data on each pixel clock.
The pixel clock defines the time available to display one pixel of information. The VS signal
defines the
refresh
frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display’s phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal
retrace
frequency.
VGA Signal Timing
The signal timings in
are derived for a 640-pixel by 480-row display using a
25 MHz pixel clock and 60 Hz ± 1 refresh.
shows the relation between each of
the timing symbols. The timing for the sync pulse width (T
PW
) and front and back porch
intervals (T
FP
and T
BP
) are based on observations from various VGA displays. The front
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
Table 6-2:
640x480 Mode VGA Timing
Symbol
Parameter
Vertical Sync
Horizontal Sync
Time
Clocks
Lines
Time
Clocks
T
S
Sync pulse time
16.7 ms
416,800
521
32 µs
800
T
DISP
Display time
15.36 ms
384,000
480
25.6 µs
640
T
PW
Pulse width
64 µs
1,600
2
3.84 µs
96
T
FP
Front porch
320 µs
8,000
10
640 ns
16
T
BP
Back porch
928 µs
23,200
29
1.92 µs
48
Figure 6-3:
VGA Control Timing
T
fp
T
di
s
p
T
S
T
pw
T
b
p
UG2
3
0_c6_0
3
_021706