NAIM NDX - User Manual - page 6
Copyright Naim Audio 2010
Page 6 of 8
When it comes to choosing how to implement the low-
pass filter, it is all a matter of taste and how well you can
implement the method you choose. Having listened to IIR
(infinite impulse response) and FIR (finite impulse response)
implementations of filters with identical amplitude and phase
responses, we found that we prefer the IIR implementation.
Even though, in a perfect world, FIR should be able to
implement any IIR response to the resolution of the DACs,
we found that processing loads, arithmetic noise, etc had
greater influence on sound quality than the phase errors
that IIR filters inherently introduce.
The NDX uses the same 16x oversampling filter as the Naim
DAC, which is implemented in the SHARC processor. The
chosen filter is a modified Butterworth to which additional
poles have been added to prevent too much phase shift
occurring within the audio band. To ensure both low
arithmetic noise (fewer additions and multiplications that
cause rounding) and low power supply noise (since the
DSP draws less current when it isn’t calculating) the filter
is implemented as efficiently as possible, using only five
lines of assembly code.
In addition, all code that runs in the SHARC processor
has been tuned by listening tests to maximise sound
quality. With every increase in number crunching the
DSP consumes more power, and the more power the
DSP consumes the greater the power supply noise. By
optimising the DSP algorithms and controlling the way the
data is buffered, power supply noise is kept to a minimum
– to the benefit of audio performance.
Master clock
The stability or noise of a DAC’s master clock has a direct
influence on the audio output. For example, if the clock
frequency were to increase momentarily by one per cent
then the analogue output frequency would increase by
the same amount. So the NDX’s master clock has been
designed to oscillate with extremely low noise. There
are many types of clock frequency instability with many
different causes but by careful design these influences
can be minimised.
Phase noise is random and can be caused by internal
and external influences on the clock. Power supply noise,
for instance, can influence its oscillation, so in the NDX
the master clock has its own voltage regulator to prevent
external noise influencing stability. But poor printed circuit
board (PCB) layout can introduce power supply noise
even when a regulator is used. The NDX PCB has six
layers and is laid out such that circulating currents are
kept local. All decoupling capacitors are connected with
short, wide tracks to ensure low impedance and less HF
noise on the power supply lines.
When the NDX is playing audio via S/PDIF, the source
of the S/PDIF signal is the master and the NDX’s master
clock must, on average, match the frequency of the
source clock. Some products achieve this either by using
an asynchronous sample rate converter (ASRC) or a
voltage-controlled crystal oscillator (VCXO) together with
a Phase Locked Loop (PLL).
ASRCs can work well but they rely on considerable
mathematic processing, which will cause problems if
not implemented very carefully. There are no ASRC
chips on the market that can convert arbitrary input
sample frequency to high enough frequencies that the
analogue output filter can be kept fairly simple. This
means that you still have to oversample the data before
the DAC, so you might as well do that properly from
the outset and avoid the ASRC entirely. Moreover, since
ASRC relies on averaging the incoming sample rate,
not all jitter will be removed. The NDX uses the built-in
ASRC in the SHARC DSP only when the incoming data
rate is outside the S/PDIF spec. The SHARC’s ASRC
has an arithmetic noise level of –128dB and so it is only
used in these exceptional circumstances.
The Naim DSP filter response and passband ripple,
input sample rate 48kHz