National Instruments NI 5782R User manual and specifications - page 15
NI 5782R User Manual and Specifications
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© National Instruments
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15
Tip
Click the Clean Up Diagram button on the toolbar to cleanly organize the VI
block diagrams.
16. Save the VI as
5782SampleAcq (FPGA).vi
.
17. Click the Run button. LabVIEW creates a default build specification and begins compiling
the VI. The Generating Intermediate Files window opens and displays the code
generation progress. Next, the Compilation Status window opens and displays the
progress of the compilation. The compilation takes several minutes.
18. Click Close in the Compilation Status window.
19. Save and close the VI.
20. Save the project.
Creating a Host VI
1.
In the Project Explorer window, right-click My Computer and select New»VI to open a
blank VI.
2.
Select Window»Show Block Diagram to open the VI block diagram.
3.
Add the Open FPGA VI Reference function, located on the FPGA Interface palette, to the
block diagram.
4.
Drag and drop your 5782SampleAcq(FPGA).vi into the Open FPGA VI Reference. The
target name appears under the Open FPGA VI Reference function in the block diagram.
5.
In the block diagram, add a While Loop to the right of the Open FPGA VI Reference
function.
6.
Right-click the conditional terminal inside the While Loop and select Create Control to
create a STOP button on the VI front panel window.
7.
Add the Read/Write Control function, located on the FPGA Interface palette, inside the
While Loop.
8.
Wire the FPGA VI Reference Out output terminal of the Open FPGA VI Reference
function to the FPGA VI Reference In input terminal of the Read/Write Controlfunction.
9.
Wire the error out terminal of the Open FPGA VI Reference function to the error in
control of the Read/Write Control function.
10. Configure the Read/Write Control function by clicking the terminal section labeled
Unselected, and selecting IO Module/AI 0 N-1.
11. Click and drag the bottom edge of the control edge to expose the other signals, AI 0
N-1...AI 1 N, to the Read/Write Control function.
12. Wire indicators to each output terminal of the IO Module\AI 0 N-1...AI 1 N.
13. Add the Close FPGA VI Reference function, located on the FPGA Interface palette, to the
right of the While Loop on the block diagram.
14. Wire the FPGA VI Reference Out terminal of the Read/Write Control function to the
FPGA VI Reference In terminal of the Close FPGA VI Reference function.
15. Wire the error out terminal of the Read/Write Control function to the error in terminal of
the Close FPGA VI Reference function.