P&E Microcomputer Systems XPC560P EVB User Manual - page 37
xPC560P EVB User Manual
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J19 – VREG Voltage Enable
Controls whether power is provided to the “VDD VREG” pins on the
MPC560xP processor.
J20 – FLA0FLA1 Voltage Enable
Controls whether power is provided to the “VDD” pin 69 on the MPC560xP
processor.
4.3
System Clock Configuration
The xPC560P Mini-Modules support the usage of crystal clock sources as
well as external clock sources.
J10 – Crystal clock source enable
2+3
Debug port(s) are configured for 3.3V logic
Jumper Setting
Effect
On (default)
MPC560xP “VDD VREG” pins are connected to 3.3V
or 5V (determined by J3)
Off
MPC560xP “VDD VREG” pins are left disconnected
Jumper Setting
Effect
On (default)
MPC560xP “VDD” pin 69 is connected to 3.3V or 5V
(determined by J3)
Off
MPC560xP “VDD” pin 69 is left disconnected