IBM PPC750FX User Manual - page 65
of
116
Evaluation Board Manual
Preliminary
PPC750FX Evaluation Board
750FXebm_ch10.fm
June 10, 2003
Connectors
Page 65 of 115
24
addr_pod1 – D7
DEV_ADR(7)
25
addr_pod0 – D6
DEV_ADR(22)
26
addr_pod1 – D6
DEV_ADR(6)
27
addr_pod0 – D5
DEV_ADR(21)
28
addr_pod1 – D5
DEV_ADR(5)
29
addr_pod0 – D4
DEV_ADR(20)
30
addr_pod1 – D4
DEV_ADR(4)
31
addr_pod0 – D3
DEV_ADR(19)
32
addr_pod1 – D3
DEV_ADR(3)
33
addr_pod0 – D2
DEV_ADR(18)
34
addr_pod1 – D2
DEV_ADR(2)
35
addr_pod0 – D1
DEV_ADR(17)
36
addr_pod1 – D1
DEV_ADR(1)
37
addr_pod0 – D0
DEV_ADR(16)
38
addr_pod1 – D0
DEV_ADR(0)
Table 10-10. System Controller Device Address Signals—J14 (Continued)
Pin
Analyzer
Signal Name