IBM PPC750FX User Manual - page 88
Evaluation Board Manual
PPC750FX Evaluation Board
Preliminary
CPLD Programming
Page 88 of 115
750FXebm_ch11.fm
June 10, 2003
-- Register 4
if ((badr[2..0] == B"100")) then
BoardRev_sel = !fpga_cs_n;
data_sel[] = 4;
else
BoardRev_sel = gnd;
end if;
-- read logic
bux_muxer.data[0][7..0] = PLDversion[7..0];
bux_muxer.data[1][7..0] = Register1.q[7..0];
bux_muxer.data[2][7..0] = Register2.q[7..0];
bux_muxer.data[3][7..0] = Register3.q[7..0];
bux_muxer.data[4][7..0] = BoardRev[7..0];
bux_muxer.sel[] = data_sel[];
-- output enable for read from FPGA only
read_oe = !cstiming_n & ldevR_W_n &
(Register1_sel # Register2_sel # Register3_sel
# PLDversion_sel # BoardRev_sel);
dev_ad[0] = TRI( bux_muxer.result[0], read_oe );
dev_ad[1] = TRI( bux_muxer.result[1], read_oe );
dev_ad[2] = TRI( bux_muxer.result[2], read_oe );
dev_ad[3] = TRI( bux_muxer.result[3], read_oe );
dev_ad[4] = TRI( bux_muxer.result[4], read_oe );
dev_ad[5] = TRI( bux_muxer.result[5], read_oe );
dev_ad[6] = TRI( bux_muxer.result[6], read_oe );
dev_ad[7] = TRI( bux_muxer.result[7], read_oe );
END;