IBM PPC750FX User Manual - page 74
Evaluation Board Manual
PPC750FX Evaluation Board
Preliminary
CPLD Programming
Page 74 of 115
750FXebm_ch11.fm
June 10, 2003
~TMS~
15
Input
write_n
16
Output
uart_cs_n
17
Output
VCCIO1
18
Power
nvram_cs_n
19
Output
led1
20
Output
led_red_n
21
Output
ignore_fans_n
22
Input
mpp0_sreset_n
23
Input
cpu1_chkstop_n
24
Input
sysreset
25
Output
GND
26
Gnd
dev_adr[5]
27
Bidir
dev_adr[6]
28
Bidir
dev_adr[7]
29
Bidir
sysreset_n
30
Output
mpp1_hreset_n
31
Input
NOFAN_N
32
Output
sram_cs_n
33
Output
VCCIO1
34
Power
small_flash_cs_n
35
Output
read_n
36
Output
big_flash_cs_n
37
Output
GND
38
Gnd
VCCINT
39
Power
badr[0]
40
Input
initact
41
Input
flash_n/sram_sel
42
Input
GND
43
Gnd
lcs_n[2]
44
Input
pwrgd
45
Input
switch_a
46
Input
testpin_c
47
Output
testpin_b
48
Output
testpin_a
49
Output
textpin_d
50
Output
VCCIO2
51
Power
Table 11-2. CPLD I/O Pin List (Continued)
Name
Pin
Function