IBM PPC750FX User Manual - page 98
Evaluation Board Manual
PPC750FX Evaluation Board
Preliminary
CPLD Programming
Page 98 of 115
750FXebm_ch11.fm
June 10, 2003
flash_n/sram_sel
small_flash_cs_n
5.300
5.300
flash_n/sram_sel
small_flash_hi_cs_n
5.300
5.300
flash_n/sram_sel
sram_cs_n
5.300
5.300
flash_n/sram_sel
sram_hi_cs_n
5.300
5.300
flash_n/sram_sel
textpin_d
5.500
5.500
ignore_fans_n
led_red_n
5.100
5.100
ignore_fans_n
NOFAN_N
5.100
5.100
initact
cpu_trst_n
13.900
13.900
initact
cpu0_hreset_n
11.000
10.200
initact
cpu1_hreset_n
14.300
13.900
lcs_n[0]
big_flash_cs_n
5.200
5.200
lcs_n[0]
small_flash_cs_n
5.200
5.200
lcs_n[0]
small_flash_hi_cs_n
5.200
5.200
lcs_n[0]
sram_cs_n
5.200
5.200
lcs_n[0]
sram_hi_cs_n
5.200
5.200
lcs_n[0]
textpin_d
5.400
5.400
lcs_n[1]
dev_adr[0]
8.500
8.500
lcs_n[1]
dev_adr[1]
8.500
8.500
lcs_n[1]
dev_adr[2]
8.500
8.500
lcs_n[1]
dev_adr[3]
8.500
8.500
lcs_n[1]
dev_adr[4]
8.500
8.500
lcs_n[1]
dev_adr[5]
8.500
8.500
lcs_n[1]
dev_adr[6]
8.500
8.500
lcs_n[1]
dev_adr[7]
8.500
8.500
lcs_n[1]
fpga_cs_n
5.400
5.400
lcs_n[2]
uart_cs_n
5.000
5.000
lcs_n[2]
write_n
5.800
5.800
lcs_n[3]
nvram_cs_n
15.300
15.300
lcs_n[3]
uart_cs_n
6.600
6.600
lcs_n[3]
write_n
7.400
5.100
ldev_addr[19]
small_flash_cs_n
5.200
5.200
ldev_addr[19]
small_flash_hi_cs_n
5.200
5.200
ldev_addr[19]
sram_cs_n
5.200
5.200
ldev_addr[19]
sram_hi_cs_n
5.200
5.200
ldev_addr[19]
textpin_d
5.400
5.400
ldev_addr[20]
small_flash_cs_n
5.200
5.200
ldev_addr[20]
small_flash_hi_cs_n
5.200
5.200
Table 11-6. Pin-to-Pin Signal Delay (Continued)
Source
Destination
Longest Delay (ns)
Shortest Delay (ns)