IBM PPC750FX User Manual - page 79
of
116
Evaluation Board Manual
Preliminary
PPC750FX Evaluation Board
750FXebm_ch11.fm
June 10, 2003
CPLD Programming
Page 79 of 115
11.1.2.3 framcs Logic
The following logic diagram defines the function of the logic in the
framcs
part of the CPLD:
Date: May 6, 2003
framcs.bdf
Project: top
badr0
qadr0
badr1
qadr1
badr2
qadr2
qadr2
qadr1
qadr0
VCC
sysclock
INPUT
VCC
lcs_n[3]
INPUT
VCC
sysreset
INPUT
VCC
cstiming_n
INPUT
GND
badr0
INPUT
GND
badr1
INPUT
GND
badr2
INPUT
nvram_burst_cs_n
OUTPUT
DFF
data
clock
enable
aclr
q
lpm_dff0
inst
DFF
data
clock
enable
aclr
q
lpm_dff0
inst1
DFF
data
clock
enable
aclr
q
lpm_dff0
inst2
lpm_xor0
inst7
lpm_xor0
inst8
lpm_xor0
inst9
lpm_or0
inst10
NOT
inst13
NOT
inst14