B&R Industries Provit 5000 User Manual - page 261
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Provit 5000 User’s Manual
Software • BIOS System for System Units with Socket 7 (ZIF)
DRAM Speculative Leadoff
A read request from the CPU to the DRAM controller includes the memory
address of the desired data. When Enabled, Speculative Leadoff lets the DRAM
controller pass the read command to memory slightly before it has fully decoded
the address, thus speeding up the read process.
Turn-Around Insertion
When Enabled, the chipset inserts one extra clock to the turn-around of back-to-
back DRAM cycles.
ISA Clock
You can set the speed of the AT bus to one-third or one-fourth of the CPU clock
speed.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the Video BIOS ROM at C0000h-CBFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
8/16 Bit I/O Recovery Time
The I/O recovery mechanism delays PCI I/O cycles (created by PCI hardware), so
that it can guarantee compatibility with the ISA bus. A delay of one or more bus
clock cycles can be set. These two fields let you define recovery time (in bus clock
cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for ROM memory on ISA cards.
When this area is reserved, it cannot be cached. The user information for
peripherals that need to use this area of system memory usually describes their
memory requirements.
If this option is activated, then the memory area of over 16MB cannot be used
anymore.