B&R Industries Provit 5000 User Manual - page 277
276
Provit 5000 User’s Manual
Software • BIOS System for System Units with Socket 7 (ZIF)
2.15.2 Chipset Features Setup
Elite BIOS Version
Description
00.17
00.19
BIOS Defaults
Setup Defaults
BIOS Defaults
Setup Defaults
Auto Configuration
Enabled
Enabled
Enabled
Enabled
DRAM Timing
70ns
70ns
70ns
70ns
DRAM RAS# Precharge Time
4
4
4
4
DRAM R/W Leadoff Timing
7/6
7/6
7/6
7/6
Fast RAS# to CAS# Delay
3
3
3
3
DRAM Read Burst (EDO / FPM)
X333/x444
X333/x444
X333/x444
X333/x444
DRAM Write Burst Timing
X333
X333
X333
X333
Turbo Read Leadoff
Disabled
Disabled
Disabled
Disabled
DRAM Speculative Leadoff
Disabled
Disabled
Disabled
Disabled
Turn-Around Insertion
Disabled
Disabled
Disabled
Disabled
ISA Clock
PCICLK/4
PCICLK/4
PCICLK/4
PCICLK/4
System BIOS Cacheable
Disabled
Disabled
Disabled
Disabled
Video BIOS Cacheable
Disabled
Disabled
Disabled
Disabled
8 Bit I/O Recovery Time
3
1
3
1
16 Bit I/O Recovery Time
2
1
2
1
Memory Hole at 15M-16M
Disabled
Disabled
Disabled
Disabled
Peer Concurrency
Enabled
Enabled
Enabled
Enabled
Chipset Special Features
Disabled
Enabled
Disabled
Enabled
DRAM ECC/PARITY Select
ECC
Parity
ECC
Parity
Memory Parity/ECC Check
AUTO
AUTO
AUTO
AUTO
Single Bit Error Report
Enabled
Enabled
Enabled
Enabled
L2 Cache Cacheable Size
512MB
512MB
512MB
512MB
Chipset NA# Asserted
Enabled
Enabled
Enabled
Enabled
Pipeline Cache Timing
Faster
Faster
Faster
Faster
Passive Release
Enabled
Enabled
Enabled
Enabled
Delayed Transaction
Disabled
Disabled
Disabled
Disabled
Table 164: Chipset Features Setup