B&R Industries Provit 5000 User Manual - page 263
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Provit 5000 User’s Manual
Software • BIOS System for System Units with Socket 7 (ZIF)
Pipeline Cache Timing
For secondary cache of one bank, select Faster. For a secondary cache of two
banks, select Fastest.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during passive release.
Otherwise, the arbiter only accepts another PCI master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32 bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.